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9.5 RON, 16-Channel, Differential 8-Channel, 15 V/+12 V/5 V iCMOS Multiplexers
ADG1406/ADG1407
FEATURES
9.5 on resistance @ 25C Up to 300 mA of continuous current Fully specified at 15 V/+12 V/5 V 3 V logic-compatible inputs Rail-to-rail operation Break-before-make switching action 28-lead TSSOP and 32-lead, 5 mm x 5 mm LFCSP_VQ
FUNCTIONAL BLOCK DIAGRAMS
ADG1406
S1
D
APPLICATIONS
Medical equipment Audio and video routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Communication systems
S16 1-OF-16 DECODER
07419-001
A0 A1 A2 A3 EN
Figure 1.
ADG1407
S1A DA S8A
GENERAL DESCRIPTION
The ADG1406 and ADG1407 are monolithic iCMOS(R) analog multiplexers comprising 16 single channels and eight differential channels, respectively. The ADG1406 switches one of 16 inputs to a common output, as determined by the 4-bit binary address lines (A0, A1, A2, and A3). The ADG1407 switches one of eight differential inputs to a common differential output, as determined by the 3-bit binary address lines (A0, A1, and A2). An EN input on both devices enables or disables the device. When disabled, all channels switch off. When on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. The iCMOS (industrial CMOS) modular manufacturing process combines high voltage CMOS (complementary metaloxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
S1B DB S8B 1-OF-8 DECODER
07419-002
A0 A1 A2 EN
Figure 2.
Table 1. Related Devices
Part No. ADG1206/ADG1207 Description Low capacitance, low charge injection, and low leakage 8-/16-channel 15 V multiplexers
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADG1406/ADG1407 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 15 V Dual Supply ....................................................................... 3 12 V Single Supply ........................................................................ 4 5 V Dual Supply ......................................................................... 6 Continuous Current per Channel .............................................. 7 Absolute Maximum Ratings ............................................................8 Thermal Resistance .......................................................................8 ESD Caution...................................................................................8 Pin Configurations and Function Descriptions ............................9 Typical Performance Characteristics ........................................... 13 Terminology .................................................................................... 17 Test Circuits ..................................................................................... 18 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
8/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG1406/ADG1407 SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. 1 Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANSITION Break-Before-Make Time Delay, tBBM tON (EN) tOFF (EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion (THD + N) -3 dB Bandwidth ADG1406 ADG1407 Insertion Loss CS (Off ) CD (Off ) ADG1406 ADG1407 +25C -40C to +85C -40C to +125C1 VSS to VDD 9.5 11.5 0.55 1 1.6 1.9 0.01 0.25 0.01 0.5 0.05 0.5 1 3 3 4 20 20 2.0 0.8 0.002 0.1 3 105 160 40 83 110 98 120 10 -73 -70 0.07 14 1.5 2.15 16 1.7 2.3 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ % typ Test Conditions/Comments
VDD = +13.5 V, VSS = -13.5 V, VS = 10 V, IS = -10 mA; see Figure 27 VDD = +13.5 V, VSS = -13.5 V , VS = 10 V, IS = -10 mA VDD = +13.5 V, VSS = -13.5 V, VS = 10 V, IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = 10 V; see Figure 28 VS = 10 V, VD = 10 V; see Figure 28 VS = VD = 10 V; see Figure 29
VIN = VGND or VDD
200
225 10
140 145
155 165
RL = 100 , CL = 35 pF VS = 10 V, see Figure 30 RL = 100 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 31 RL = 100 , CL = 35 pF VS = 10 V; see Figure 32 RL = 100 , CL = 35 pF VS = 10 V; see Figure 32 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 35 RL = 110 , 15 V p-p, f = 20 Hz to 20 kHz; see Figure 37 RL = 50 , CL = 5 pF; see Figure 36
60 110 0.6 8 90 45
MHz typ MHz typ dB typ pF typ pF typ pF typ
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 36 f = 1 MHz f = 1 MHz f = 1 MHz
Rev. 0 | Page 3 of 20
ADG1406/ADG1407
Parameter CD, CS (On) ADG1406 ADG1407 POWER REQUIREMENTS IDD IDD ISS VDD/VSS
1 2
+25C 115 70 0.002
-40C to +85C
-40C to +125C1
Unit pF typ pF typ A typ A max A typ A max A typ A max V min/max
Test Conditions/Comments f = 1 MHz f = 1 MHz VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V, 5 V or VDD
1 280 400 0.002 1 4.5/16.5
Temperature range for B version is -40C to +125C. Guaranteed by design, not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) +25C -40C to +85C -40C to +125C 1 0 to VDD 18 21.5 0.55 1.2 5 6 0.01 0.25 0.01 0.5 0.01 0.5 1 4 26 1.6 6.9 28.5 1.8 7.3 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns min Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = -10 mA; see Figure 27 VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = -10 mA VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V, IS = -10 mA VDD = 10.8 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 28 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 28 VS = VD = 1 V or 10 V; see Figure 29
Drain Off Leakage, ID (Off )
3 3
20 20 2.0 0.8
Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANSITION Break-Before-Make Time Delay, tBBM
0.002 0.1 4 170 250 75
VIN = VGND or VDD
310
350 30
RL = 100 , CL = 35 pF VS = 8 V; see Figure 29 RL = 100 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 31
Rev. 0 | Page 4 of 20
ADG1406/ADG1407
Parameter tON (EN) tOFF (EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth ADG1406 ADG1407 Insertion Loss CS (Off ) CD (Off ) ADG1406 ADG1407 CD, CS (On) ADG1406 ADG1407 POWER REQUIREMENTS IDD IDD VDD
1 2
+25C 145 205 112 150 10 -73 -70
-40C to +85C 250 175
-40C to +125C 1 285 200
Unit ns typ ns max ns typ ns max pC typ dB typ dB typ
Test Conditions/Comments RL = 100 , CL = 35 pF VS = 8 V; see Figure 31 RL = 100 , CL = 35 pF VS = 8 V; see Figure 31 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 35 RL = 50 , CL = 5 pF; see Figure 36
35 70 0.6 12 145 72 166 93 0.002 1 150 240 5/16.5
MHz typ MHz typ dB typ pF typ pF typ pF typ pF typ pF typ A typ A max A typ A max V min/max
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 36 f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V VSS = 0 V, GND = 0 V
Temperature range for B version: -40C to +125C. Guaranteed by design, not subject to production test.
Rev. 0 | Page 5 of 20
ADG1406/ADG1407
5 V DUAL SUPPLY
VDD = +5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted. Table 4.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On -Resistance Match Between Channels (RON) On -Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANSITION Break-Before-Make Time Delay, tBBM tON (EN) tOFF (EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion, THD + N -3 dB Bandwidth ADG1406 ADG1407 Insertion Loss CS (Off ) CD (Off ) ADG1406 ADG1407 CD, CS (On) ADG1406 ADG1407 +25C -40C to +85C -40C to +125C 1 VSS to VDD 21 25 0.6 1.3 5.2 6.4 0.01 0.25 0.01 0.5 0.01 0.5 1 3 3 4 20 20 2.0 0.8 0.002 0.1 3.5 260 435 90 230 335 205 290 10 -73 -70 0.18 29 1.7 7.3 32 1.9 7.6 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ % typ Test Conditions/Comments
VDD = +4.5 V, VSS = -4.5 V, VS = 4.5 V, IS = -10 mA; see Figure 27 VDD = +4.5 V, VSS = -4.5 V, VS = 4.5V, IS = -10 mA VDD = +4.5 V, VSS = -4.5 V, VS = 4.5 V; IS = -10 mA VDD = +5.5 V, VSS = -5.5 V VS = 4.5 V, VD = 4.5 V; see Figure 28 VS = 4.5 V, VD = 4.5 V; see Figure 28 VS = VD = 4.5 V; see Figure 29
VIN = VGND or VDD
510
565 30
400 340
445 370
RL = 100 , CL = 35 pF VS = 5 V; see Figure 30 RL = 100 , CL = 35 pF VS1 = VS2 = 5 V; see Figure 31 RL = 100 , CL = 35 pF VS = 5 V; see Figure 32 RL = 100 , CL = 35 pF VS = 5 V; see Figure 32 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 35 RL = 110 , 5 V p-p, f = 20 Hz to 20 kHz; see Figure 37 RL = 50 , CL = 5 pF; see Figure 36
40 80 1.15 10 123 62 148 88
MHz typ MHz typ dB typ pF typ pF typ pF typ pF typ pF typ
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 36 f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz
Rev. 0 | Page 6 of 20
ADG1406/ADG1407
Parameter POWER REQUIREMENTS IDD ISS VDD/VSS
1 2
+25C 0.002
-40C to +85C
-40C to +125C 1
Unit A typ A max A typ A max V min/max
Test Conditions/Comments VDD = +5.5 V, VSS = -5.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V, 5 V, or VDD
1 0.002 1 4.5/16.5
Temperature range for B version: -40C to +125C. Guaranteed by design, not subject to production test.
CONTINUOUS CURRENT PER CHANNEL
Table 5. ADG1406
Parameter CONTINUOUS CURRENT PER CHANNEL 1 15 V Dual Supply 28-Lead TSSOP 32-Lead LFCSP 12 V Single Supply 28-Lead TSSOP 32-Lead LFCSP 5 V Dual Supply 28-Lead TSSOP 32-Lead LFCSP
1
25C
85C
125C
Unit
Test Conditions/Comments VDD = +13.5 V, VSS = -13.5 V
180 300 150 260 140 245
100 150 90 130 85 130
50 60 50 55 45 55
mA max mA max VDD = 10.8 V, VSS = 0 V mA max mA max VDD = +4.5 V, VSS = -4.5 V mA max mA max
Guaranteed by design, not subject to production test.
Table 6. ADG1407
Parameter CONTINUOUS CURRENT PER CHANNEL 1 15 V Dual Supply 28-Lead TSSOP 32-Lead LFCSP 12 V Single Supply 28-Lead TSSOP 32-Lead LFCSP 5 V Dual Supply 28-Lead TSSOP 32-Lead LFCSP
1
25C
85C
125C
Unit
Test Conditions/Comments VDD = +13.5 V, VSS = -13.5 V
135 235 110 190 105 180
85 125 70 110 65 100
45 55 40 50 40 50
mA max mA max VDD = 10.8 V, VSS = 0 V mA max mA max VDD = +4.5 V, VSS = -4.5 V mA max mA max
Guaranteed by design, not subject to production test.
Rev. 0 | Page 7 of 20
ADG1406/ADG1407 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 7.
Parameter VDD to VSS VDD to GND VSS to GND Analog, Digital Inputs1 Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Table 5 and Table 6 specifications + 15%
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 8. Thermal Resistance
Package Type 28-Lead TSSOP 32-Lead LFCSP_VQ JA 97.9 27.27 JC 14 Unit C/W C/W
Continuous Current, Sx or Dx Pins Peak Current, Sx or Dx Pins (Pulsed at 1 ms, 10% Duty Cycle Maximum) 28-Lead TSSOP 32-Lead LFCSP_VQ Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature Reflow Soldering, Pb-Free Peak Temperature Time at Peak Temperature
1
ESD CAUTION
300 mA 550 mA -40C to +125C -65C to +150C 150C 260 (+0/-5)C 10 sec to 40 sec
Overvoltages at the Ax, EN, Sx, or Dx pins are clamped by internal diodes. Limit current to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
Rev. 0 | Page 8 of 20
ADG1406/ADG1407 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC NC S16 S15 S14 S13 S12 S11
2 3 4 5 6 7 8 9 27 26 25 24
VSS S8 S7 S6 S5 S4 S3 S2 S1 EN A0 A1 A2
07419-003
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
VDD
1
28
D
NC VDD NC D NC NC NC VSS
ADG1406
TOP VIEW (Not to Scale)
23 22 21 20 19 18 17 16 15
S16 S15 S14 S13 S12 S11 S10 S9
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
ADG1406
TOP VIEW (Not to Scale)
S8 S7 S6 S5 S4 S3 S2 S1
07419-004
S10 10 S9 11 GND 12 NC 13 A3 14
NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, VSS.
NC = NO CONNECT
Figure 3. ADG1406 TSSOP Pin Configuration
Figure 4. ADG1406 LFCSP Pin Configuration
Table 9. ADG1406 Pin Function Descriptions
TSSOP 1 2, 3, 13 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin No. LFCSP_VQ 31 12, 13, 26, 27, 28, 30, 32 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 29 Mnemonic VDD NC S16 S15 S14 S13 S12 S11 S10 S9 GND A3 A2 A1 A0 EN S1 S2 S3 S4 S5 S6 S7 S8 VSS D Description Most Positive Power Supply Potential. No Connect. Source Terminal 16. This pin can be an input or an output. Source Terminal 15. This pin can be an input or an output. Source Terminal 14. This pin can be an input or an output. Source Terminal 13. This pin can be an input or an output. Source Terminal 12. This pin can be an input or an output. Source Terminal 11. This pin can be an input or an output. Source Terminal 10. This pin can be an input or an output. Source Terminal 9. This pin can be an input or an output. Ground (0 V) Reference. Logic Control Input. Logic Control Input. Logic Control Input. Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. Source Terminal 1. This pin can be an input or an output. Source Terminal 2. This pin can be an input or an output. Source Terminal 3. This pin can be an input or an output. Source Terminal 4. This pin can be an input or an output. Source Terminal 5. This pin can be an input or an output. Source Terminal 6. This pin can be an input or an output. Source Terminal 7. This pin can be an input or an output. Source Terminal 8. This pin can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. The exposed pad is tied to the substrate, VSS. Drain Terminal. This pin can be an input or an output.
Rev. 0 | Page 9 of 20
GND A3 A2 NC NC A1 A0 EN
9 10 11 12 13 14 15 16
ADG1406/ADG1407
Table 10. ADG1406 Truth Table
A3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 On Switch None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Rev. 0 | Page 10 of 20
ADG1406/ADG1407
DB NC S8B S7B S6B S5B S4B S3B
2 3 4 5 6 7 8 9 27 26 25 24
VSS S8A S7A S6A S5A S4A S3A S2A S1A EN A0 A1 A2
07419-036
32 31 30 29 28 27 26 25
VDD
1
28
DA
NC DB NC VDD NC DA NC VSS
ADG1407
TOP VIEW (Not to Scale)
23 22 21 20 19 18 17 16 15
S8B S7B S6B S5B S4B S3B S2B S1B
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
ADG1407
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
S8A S7A S6A S5A S4A S3A S2A S1A
S1B 11 GND 12 NC 13 NC 14
NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, VSS.
NC = NO CONNECT
Figure 5. ADG1407 TSSOP Pin Configuration
Figure 6. ADG1407 LFCSP_VQ Pin Configuration
Table 11. ADG1407 Pin Function Descriptions
TSSOP 1 2 3, 13, 14 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin No. LFCSP_VQ 29 31 11, 12, 13, 26, 28, 30, 32 1 2 3 4 5 6 7 8 9 10 14 15 16 17 18 19 20 21 22 23 24 25 27 Mnemonic VDD DB NC S8B S7B S6B S5B S4B S3B S2B S1B GND A2 A1 A0 EN S1A S2A S3A S4A S5A S6A S7A S8A VSS DA Description Most Positive Power Supply Potential. Drain Terminal B. This pin can be an input or an output. No Connect. Source Terminal 8B. This pin can be an input or an output. Source Terminal 7B. This pin can be an input or an output. Source Terminal 6B. This pin can be an input or an output. Source Terminal 5B. This pin can be an input or an output. Source Terminal 4B. This pin can be an input or an output. Source Terminal 3B. This pin can be an input or an output. Source Terminal 2B. This pin can be an input or an output. Source Terminal 1B. This pin can be an input or an output. Ground (0 V) Reference. Logic Control Input. Logic Control Input. Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. Source Terminal 1A. This pin can be an input or an output. Source Terminal 2A. This pin can be an input or an output. Source Terminal 3A. This pin can be an input or an output. Source Terminal 4A. This pin can be an input or an output. Source Terminal 5A. This pin can be an input or an output. Source Terminal 6A. This pin can be an input or an output. Source Terminal 7A. This pin can be an input or an output. Source Terminal 8A. This pin can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. The exposed pad is tied to the substrate, VSS. Drain Terminal A. This pin can be an input or an output.
Rev. 0 | Page 11 of 20
07419-037
GND A2 NC NC NC A1 A0 EN
S2B 10
9 10 11 12 13 14 15 16
ADG1406/ADG1407
Table 12. ADG1407 Truth Table
A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 On Switch Pair None 1 2 3 4 5 6 7 8
Rev. 0 | Page 12 of 20
ADG1406/ADG1407 TYPICAL PERFORMANCE CHARACTERISTICS
16 14 12 VDD = +10V VSS = -10V 18 VDD = +13.5V VSS = -13.5V 15 VDD = +12V VSS = -12V
ON RESISTANCE ()
ON RESISTANCE ()
10 8 6 4 2 VDD = +15V VSS = -15V VDD = +16.5V VSS = -16.5V
12
TA = +125C TA = +85C TA = +25C
9
6
TA = -40C
3
07419-006
0 -16.5 -13.5 -10.5 -7.5 -4.5
TA = 25C IS = -10mA
-1.5
1.5
4.5
7.5
10.5 13.5 16.5
0 -15
-10
-5
0 VS, VD (V)
5
10
15
VS, VD (V)
Figure 7. On Resistance as a Function of VD (VS), Dual Supply
35 30 25 20 15 10 5 0 -7 TA = 25C IS = -10mA -5 -3 -1 1 3 5 7 VS, VD (V) VDD = +7V VSS = -7V VDD = +5.5V VSS = -5.5V
07419-007
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures, 15 V Dual Supply
30
VDD = +3.V VSS = -3.V 25 VDD = +4.5V VSS = -4.5V VDD = +5.0V VSS = -5.0V
ON RESISTANCE ()
ON RESISTANCE ()
20
TA = +125C
15
TA = +85C TA = +25C
10
TA = -40C
5
07419-010
VDD = +5V VSS = -5V 0 -5 -4 -3 -2 -1 0 VS, VD (V) 1 2 3 4 5
Figure 8. On Resistance as a Function of VD (Vs), Dual Supply
40 35 30 VDD = +5V VSS = 0V 25
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures, 5 V Dual Supply
20
ON RESISTANCE ()
ON RESISTANCE ()
25 20 15 10
VDD = +8V VSS = 0V VDD = +12V VSS = 0V
TA = +125C 15 TA = +85C 10 TA = +25C TA = -40C 5
VDD = +10.8V VSS = 0V
0
TA = 25C IS = -10mA 0 1.5 3.0 4.5 6.0
07419-008
5
0
7.5
9.0
10.5
12.0 13.5
15.0
0
2
4
6 VS, VD (V)
8
10
12
VS, VD (V)
Figure 9. On Resistance as a Function of VD (VS), Single Supply
Figure 12. On Resistance as a Function of VD (VS) for Different Temperatures, 12 V Single Supply
Rev. 0 | Page 13 of 20
07419-011
VDD = +15V VSS = 0V
VDD = +13.2V VSS = 0V
VDD = +12V VSS = 0V
07419-009
VDD = +15V VSS = -15V
ADG1406/ADG1407
1.0 0.8 0.6 LEAKAGE CURRENT (nA) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 0 10 20 30 40 50 60 70 80 IS (OFF) +- ID (OFF) +- IS (OFF) -+ ID (OFF) -+ ID, IS (ON) ++ ID, IS (ON) --
07419-012
1.4 VDD = +15V VSS = -15V VBIAS = +10V/-10V LEAKAGE CURRENT (nA) 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0 20 40 60 80 100 120
07419-015
VDD = +12V VSS = 0V VBIAS = +1V/+10V
IS (OFF) +- ID (OFF) +- IS (OFF) -+ ID (OFF) -+ ID, IS (ON) ++ ID, IS (ON) --
TEMPERATURE (C)
TEMPERATURE (C)
Figure 13. Leakage Current as a Function of Temperature (up to 85C), 15 V Dual Supply
8 6 4 2 0 -2 -4 -6 -8 -10 0 20 40 60 80 100 120 IS (OFF) +- ID (OFF) +- IS (OFF) -+ ID (OFF) -+ ID, IS (ON) ++ ID, IS (ON) --
07419-013
Figure 16. Leakage Current as a Function of Temperature, 12 V Single Supply
160
VDD = +15V VSS = -15V VBIAS = +10V/-10V
140 120 100
IDD (A)
TA = 25C IDD PER LOGIC INPUT
LEAKAGE CURRENT (nA)
80 60 40 20 0 VDD = +12V VSS = 0V VDD = +5V VSS = -5V 0 1.5 3.0 4.5 6.0
VDD = +15V VSS = -15V
7.5
9.0
10.5
12.0
13.5
15.0
TEMPERATURE (C)
LOGIC LEVEL (Ax, EN) (V)
Figure 14. Leakage Current as a Function of Temperature, 15 V Dual Supply
7 6 5 VDD = +5V VSS = -5V VBIAS = +4.5V/-4.5V IS (OFF) +- ID (OFF) +- IS (OFF) -+ ID (OFF) -+ ID, IS (ON) ++ ID, IS (ON) - -
Figure 17. IDD vs. Logic Level
100 TA = 25C 80 60 40 20 0 -20 -40
07419-017
VDD = +15V VSS = -15V
LEAKAGE CURRENT (nA)
4 3 2 1 0 -1 -2
CHARGE INJECTION (pC)
VDD = +5V VSS = -5V VDD = +12V VSS = 0V
07419-014
-3 -4 0 20 40 60 80 100 120
-60 -80 -15 -10 -5 0 VS (V) 5 10 15
TEMPERATURE (C)
Figure 15. Leakage Current as a Function of Temperature, 5 V Dual Supply
Figure 18. Charge Injection vs. Source Voltage
Rev. 0 | Page 14 of 20
07419-016
ADG1406/ADG1407
350 300 250 VDD = +5V VSS = +5V
CROSSTALK (dB)
0 VDD = +15V VSS = -15V TA = 25C ADJACENT CHANNELS (S1A TO S2A)
-20
-40
TIME (ns)
200 150 100 50 0 -40
VDD = +12V VSS = 0V
-60
-80 ADJACENT SWITCHES (S1A TO S1B)
VDD = +15V VSS = -15V
07419-018
-100
-20
0
20
40
60
80
100
120
10k
TEMPERATURE (C)
100k 1M 10M FREQUENCY (Hz)
100M
1G
Figure 19. Transition Time vs. Temperature
0 0
Figure 22. ADG1407 Crosstalk vs. Frequency
-20
VDD = +15V VSS = -15V TA = 25C
INSERTION LOSS (dB)
-0.5 -1.0
OFF ISOLATION (dB)
-40
-1.5 -2.0 -2.5 -3.0 -3.5
-60
-80
-100
VDD = +15V VSS = -15V TA = 25C
07419-022
10k
07419-019
-120 1k
100k 1M 10M FREQUENCY (Hz)
100M
1G
-4.0 100
1k
10k 100k 1M FREQUENCY (Hz)
10M
100M
Figure 20. Off Isolation vs. Frequency
0.14
Figure 23. ADG1406 On Response vs. Frequency
-10 -30 -50
VDD = +15V VSS = -15V TA = 25C
VS = 20V p-p 0.12 0.10 VDD = +15V VSS = -15V TA = 25C RL = 100
CROSSTALK (dB)
THD + N (%)
-70 -90 -110 -130
07419-020
0.08 VS = 15V p-p 0.06 0.04 0.02 0
VS = 10V p-p
07419-023
-150 1k
10k
100k 1M 10M FREQUENCY (Hz)
100M
1G
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
Figure 21. ADG1406 Crosstalk vs. Frequency
Figure 24. THD + N vs. Frequency, 15 V Dual Supply
Rev. 0 | Page 15 of 20
07419-021
-120 1k
ADG1406/ADG1407
1.2 0 VDD = +15V VSS = -15V TA = 25C V p-p = 0.63V
1.0
VS = 10V p-p VDD = +5V VSS = -5V TA = 25C RL = 110
-20
0.8
-40
THD + N (%)
ACPSRR (dB)
0.6
-60
NO DECOUPLING CAPACITORS
0.4
-80
0.2
VS = 5V p-p VS = 2.5V p-p
07419-024
-100
DECOUPLING CAPACITORS ON SUPPLIES
0
2
4
6
8
10
12
14
16
18
20
1k
FREQUENCY (kHz)
10k 100k FREQUENCY (Hz)
1M
10M
Figure 25. THD + N vs. Frequency, 5 V Dual Supply
Figure 26. ACPSRR vs. Frequency
Rev. 0 | Page 16 of 20
07419-025
0
-120 100
ADG1406/ADG1407 TERMINOLOGY
RON Ohmic resistance between the D and S terminals. RON Difference between the RON of any two channels. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. IS (Off) Source leakage current when the switch is off. ID (Off) Drain leakage current when the switch is off. ID, IS (On) Channel leakage current when the switch is on. VD, VS Analog voltage on Terminal D and Terminal S. CS (Off) Channel input capacitance for the off condition. CD (Off) Channel output capacitance for the off condition. CD, CS (On) On switch capacitance. CIN Digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and the switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and the switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. tBBM Off time measured between the 80% points of the switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL, IINH Input current of the digital input. IDD Positive supply current. ISS Negative supply current. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. ACPSRR (AC Power Supply Rejection Ratio) Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.
Rev. 0 | Page 17 of 20
ADG1406/ADG1407 TEST CIRCUITS
V
IS (OFF) A ID (OFF) A
07419-026
ID (ON) NC S D A
07419-027
S
D IDS
07419-125
S
D
VS
VS
VD
NC = NO CONNECT
VD
Figure 27. On Resistance
Figure 28. Off Leakage
Figure 29. On Leakage
VDD 3V ADDRESS DRIVE (VIN) 0V 50% 50%
VSS
tr < 20ns tf < 20ns
VIN
VDD A0 50 A1 A2 A3
VSS S1 S2 TO S15 S16 VS16 OUTPUT D GND 300 35pF
07419-028
VS1
tTRANSITION
tTRANSITION
90%
ADG14061
2.4V EN
OUTPUT
90%
1SIMILAR
CONNECTION FOR ADG1407.
Figure 30. Address to Output Switching Times, tTRANSITION
VDD 3V ADDRESS DRIVE (VIN) 0V VIN 50 VSS
VDD A0 A1 A2 A3
VSS S1 S2 TO S15 S16 VS
80% OUTPUT
80% 2.4V
ADG14061
EN GND D
OUTPUT
300
35pF
07419-029
tBBM
1SIMILAR CONNECTION FOR ADG1407.
Figure 31. Break-Before-Make Delay, tBBM
VDD 3V ENABLE DRIVE (VIN) 0V 50% 50% VSS
VDD A0 A1 A2 A3
VSS S1 S2 TO S16 VS
tON (EN)
0.9VOUT OUTPUT
tOFF (EN)
0.9VOUT VIN 50
ADG14061
EN GND D
OUTPUT
300
35pF
07419-030
1SIMILAR CONNECTION FOR ADG1407.
Figure 32. Enable Delay, tON (EN), tOFF (EN)
Rev. 0 | Page 18 of 20
ADG1406/ADG1407
VDD VSS VDD A0 A1 VIN A2 A3 RS VOUT QINJ = CL x VOUT VOUT VS VIN VSS
3V
ADG14061
S EN GND D CL 1nF VOUT
1SIMILAR CONNECTION FOR ADG1407.
Figure 33. Charge Injection
VDD 0.1F
VSS 0.1F NETWORK ANALYZER
VDD 0.1F NETWORK ANALYZER VOUT RL 50
VSS 0.1F
VDD S
VSS
VDD S1
50 D
50 VS VOUT
07419-031
VSS
D S2 VS
R 50
GND
RL 50
GND
07419-032
OFF ISOLATION = 20 log
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 34. Off Isolation
Figure 36. Channel-to-Channel Crosstalk
VDD 0.1F
VSS 0.1F
VDD VSS 0.1F AUDIO PRECISION
VDD S
VSS
NETWORK ANALYZER
0.1F
50 VS D RL 50 VOUT
IN
VDD S
VSS
RS VS V p-p RL 10k VOUT
07419-035
GND
D VIN GND
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
07419-033
Figure 35. Bandwidth
Figure 37. THD + Noise
Rev. 0 | Page 19 of 20
07419-034
VOUT
VOUT VS
ADG1406/ADG1407 OUTLINE DIMENSIONS
9.80 9.70 9.60
28
15
4.50 4.40 4.30
1 14
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 38. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30 12 MAX
9
0.25 MIN 3.50 REF
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG1406BRUZ 1 ADG1406BRUZ-REEL71 ADG1406BCPZ-REEL71 ADG1407BRUZ1 ADG1407BRUZ-REEL71 ADG1407BCPZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Description 28-Lead Thin Shrink Small Outline Package [TSSOP] 28-Lead Thin Shrink Small Outline Package [TSSOP] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 28-Lead Thin Shrink Small Outline Package [TSSOP] 28-Lead Thin Shrink Small Outline Package [TSSOP] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
011708-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Package Option RU-28 RU-28 CP-32-2 RU-28 RU-28 CP-32-2
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07419-0-8/08(0)
Rev. 0 | Page 20 of 20

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